1. Field of the Invention
This invention relates to improvements to sense amplifiers for random access memories.
2. Background
Random Access Memories (RAMs) are very common storage devices in high technology products. RAMs comprise cache memories in many computers, both internal to the processor and on the computer motherboard. Typically RAMs are arranged as arrays of individually addressable memory cells. The cells are organized in rows and columns. For example, an 8k RAM chip, which has 8k memory cells, is typically an array of 1024 rows by 8 columns.
FIG. 1 shows column M of a typical N row RAM array. Cells M1 through MN are data storage units, typically comprised of flip flops optimized for reduced power consumption and area. Each row of cells has a row select line. The first cell of each column is connected to Row Select 1, and the Nth cell of each row is connected to Row Select N. Each column of cells also has a column select line. All of the cells in Column M have Column Select M (not shown), and all of the cells in Column (M+1) have Column Select (M+1). By selectively asserting row and column selects, each cell can be individually addressed.
The cells in each column are connected to a column bit line and an inverse column bit line. All cells in column M are connected to a column bit line MBIT and an inverse column bit line MBITX, MBITX having the inverse value of MBIT during read and write operations. During a read operation of a cell in Column M, the cell places the stored data value, either a logic one or a logic zero, on the MBIT line and places the inverse of the stored data value on the MBITX line. For example, if the stored value in the cell is a logic one, the cell places logic one on the MBIT line and logic zero on the MBITX line. During a write operation to a cell in Column M, the value to be written into the cell is placed on the MBIT line and the inverse of the value to be written is placed on the MBITX line. For example, if the value to be written is a logic zero, logic zero is placed on the MBIT line and logic one is placed on the MBITX line.
During a read operation, a sense amplifier connected to each column senses the difference in voltage or current between the MBIT and MBITX lines, amplifies the result, and places the result onto the MOUT and MOUTX lines. The typical sense amplifier senses the difference (either in voltage or current) of the lines on the corresponding MBIT and MBITX lines. The magnitude of the voltage difference in the MBIT and MBITX lines is typically a function of the RAM cell drain current and bit line capacitance. However, the magnitude of the current difference in the MBIT and MBITX lines is typically not dependent on the bit line capacitance. The sense amplifier amplifies to standard output levels the line difference, and the resulting difference is reflected on the MOUT and MOUTX lines. The MOUT line reflects the value stored in the memory cell and the MOUTX line reflects the inverse of the same value.
Referring to FIG. 1, two PMOS transistors, T1 and T2, act as loads for the MBIT and MBITX lines, establishing a near Vcc voltage on each line when the transistors T1 and T2 are on. The source nodes of T1 and T2 are connected to Vcc (power) and the drain nodes are connected to MBIT and MBITX, respectively. The gate nodes of T1 and T2 are connected together and connected to a PCHG (precharge) line.
PCHG is active typically when no write operation is occurring. By precharging the bit lines, the effect of the bit line capacitance on voltage is reduced during reads of the memory cell values to decrease the amount of time for the MBIT and MBITX lines to reach the correct values, thereby decreasing access times.
As the number of rows in a RAM array increase as memories get larger with newer semiconductor technologies, the MBIT and MBITX line capacitance increases. Each bit line interfaces with many cells, and consequently has parasitic capacitance much larger than the cell capacitance. When the cell is selected, the charge stored in the cell is shared with the parallel bit line capacitance, creating only a small difference on the MBIT and MBITX lines. A sense amplifier is designed to sense the small differences in current or voltage of the bit lines and amplify the difference to normal logic levels. For sense amplifiers that read directly from the MBIT and MBITX lines, the increased line capacitance of very large RAM arrays creates decreased voltage differences, causing an increase in the detection time and hence an increase in the access time. A sense amplifier that is independent of the line capacitance is needed for very large and fast RAM arrays.
FIG. 2 shows a typical prior art current sense amplifier circuit that typically operates independent of the bit line capacitances. Transistors T5, T6, T8 and T9 perform the sense operation. Transistors T3, T4, T5, and T6 perform the amplify operation. The column bit lines are ABIT and ABITX.
The prior art current sense amp of FIG. 2 is typically used in the RAM array configuration of FIG. 1. The bit lines ABIT and ABITX connect to the bit lines MBIT and MBITX of FIG. 1, respectively. A read enable line, ARE, of FIG. 2 connects to the MRE line of FIG. 1. An ARWX line (Not Read Enable and Not Write Enable) of FIG. 2 is formed by logically ANDing the inverse of the ARE line with the inverse of the MWE line.
The source node of PMOS transistor T5 is connected to the ABIT line. The drain node of T5 is connected to the drain node of NMOS transistor T3 and to an AOUT line. The gate nodes of T3 and T5 are connected together and to an AOUTX line.
The source node of PMOS transistor T6 is connected to the ABITX line. The drain node of T6 is connected to the drain node of NMOS transistor T4 and to the AOUTX line. The gate nodes of T4 and T6 are connected together and to the AOUT line.
The source nodes of T3 and T4 are connected to the drain node of NMOS transistor T7. The source node of T7 is connected to Vss (ground). The gate node of T7 is connected to a read enable line, ARE.
The drain node of NMOS transistor T8 is connected to the AOUT line. The drain node of NMOS transistor T9 is connected to the AOUTX line. The source nodes of T8 and T9 are connected to Vss. The gate nodes are T8 and T9 are connected together and connected to the ARWX line. The ARWX line is active only when there is not an active read or write operation occurring.
Prior to a read operation and not during a write operation, the ARE line is low, the ARWX line is high and the bit lines ABIT and ABITX are precharged to approximately Vcc by the PCHG line through the transistors T1 and T2 of FIG. 1. T8 and T9 are turned ON by the ARWX line while T7 is turned OFF by the ARE line. As a result, the output lines AOUT and AOUTX are pulled down to approximately Vss through T8 and T9.
The row and column selects become active, selecting a particular memory cell, starting the sensing operation. As shown in FIG. 2, the difference between the current I1 which flows through T5 and T8 and the current I2 which flows through T6 and T9 depends on the value of the data in the memory cell and may be expressed as .DELTA.I. The resulting voltage difference between the output lines AOUT and AOUTX may be expressed as .DELTA.V. The gate voltage of T6 is raised by .DELTA.V, I2 is consequently reduced, and the .DELTA.V increases.
The ARE line transitions high, causing the ARWX line to transition low, starting the amplifying operation. T8 and T9 turn OFF, T7 turns ON. The cross-coupled inverter circuit (T3, T4, T5 and T6) amplifies .DELTA.V to the standard output level. For example, if the value in the memory cell is a logic one, the ABIT line voltage will be greater than the ABITX line voltage. This causes T5 to be ON, T3 to be OFF, T6 to be OFF and T4 to be ON. Since the AOUT and AOUTX lines were pulled down prior to the start of the read operation, at least one of the lines must transition the full rail to Vcc.
The prior art sense amplifier of FIG. 2 reduces the effect of bit line capacitance on the access times of the RAM array by sensing the difference in current on the ABIT and ABITX lines. However, access times are limited by the time it takes for AOUT or AOUTX to transition the full rail from logic zero to logic one. In addition, the prior art sense amplifier uses significant amounts of silicon area, seven transistors per sense amplifier, and one sense amplifier per column in the RAM array. The prior art sense amplifier also uses significant amounts of power when not performing a read operation. When ARE is not active (i.e., when no read operation is active) T8 and T9 are ON, with large amounts of current flowing through the transistors.